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1 Reply
- Altera_Forum
Honored Contributor
The same as any other block
i.e block declaration is:
Instantiation in a top levelis:COMPONENT sopc_block IS PORT ( ... this_is_an_input_conduit_end : IN STD_LOGIC; ... ); END COMPONENT
If you want a complete example you can connect your sopc block in a top level schematic, then use Quartus to automatically generate the VHDL file, so you can see how to fully instantiate the block. RegardsENTITY top_level_hdl IS PORT ( ... top_level_signal : IN_STD_LOGIC; ... ); sopc_inst : sopc_block PORT MAP( ... this_is_an_input_conduit_end =>top_level_signal, ... );