Instantiating LPM Functions in VHDL: parallel adder

Hello guys.. ended up with

function slv_to_alteras_stupid_2d_type( a : std_logic_vector; b : std_logic_vector) return altera_mf_logic_2D is     
variable ret : altera_mf_logic_2D(0 downto 0, (a'high-a'low) downto 0); -- the two inputs have the same size but can have different subsciript: a(16 downto 1), b(18 downto 3)
variable j: integer :=0;
begin
for i in a'range loop        
ret(0,j) := a(i);
j:=j+1;
end loop;
for i in b'range loop        
j:=0;      
ret(1,j) := b(i);
j:=j+1;
end loop;          
return ret;      
end function;

my_par_add : parallel_add
generic map (...)
port map(clk=>my_clock,
              data=>slv_to_altera2d_type(('0' & bus1), bus2))
               result=> dataout);

Actual expression (function call "slv_to_altera_2d_type") of formal "data" is not globally static