Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Instantiating LPM Functions in VHDL: parallel adder

Hello guys... I'm trying instatniating some altera MF directly in my top design. From what I have understand I have two use two libraries: library altera_mf; use altera_mf.altera_mf.c...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

a std_logic_vector is an array of std_logic.

Your method is the best way.

But the other bits of an Input must be connected to something, even if it is '0' or '1', otherwise it is and error.