Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Instantiating LPM Functions in VHDL: parallel adder

Hello guys... I'm trying instatniating some altera MF directly in my top design. From what I have understand I have two use two libraries: library altera_mf; use altera_mf.altera_mf.c...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Thank you tricky. I ended up with your function suggestion.

One more thing, I have an entity that has a std_logic_vector input. By the way this time I have to assign it only a std_logic signal that is on output of another entity. the question is: Is it possible to do something like: 

stdLogicVectorIn(0)=>stdLogic

And then left without assignement the other elements of stdLogicVectorIn ?

There is a better way ?

Thank you guys !! Your help is really appreciated !