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I wouldn't call Altera's std_logic_2D type stupid. Until VHDL 2008 you could not use a 1Dx1D array in a generic way (as one dimension has to be fixed). The 2D is both elegant and pure. Altera's (and other FPGA vendors, EDA vendors included) fault was not to provide a standard library for it. With VHDL 2008 you can declare a 1D array of unconstrained std_logic_vector. And I certainly recommend this. Unfortunately I have too much legacy code to convert. (Altera did not support this either until a few versions of Quartus back, and then it once disappeared and reappeared)
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Ok, not stupid, like you said its more laziness on the part of altera.
It could probably have put people off using the blocks.
Honored Contributor
