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Hello guys...
I'm trying instatniating some altera MF directly in my top design.
From what I have understand I have two use two libraries:
library altera_mf;
use altera_mf.altera_mf.components.all;
library lpm;
use lpm.lpm_components.all;
The first libray is used to avoid the components declarations and the second is used to instantiate directly the lpm objects.
So, as I want to use a parallel adder, I wrote:
parallel_add_inst : parallale_add
GENERIC MAP(....)
PORT MAP(...);
By the way, looking at the Integer Arithmetic Megafunctions User
Guide, the port map of the parallel adder is:
data:in altera_mf_logic_2D(size - 1 downto 0,width- 1 downto 0);
clock : in std_logic := '1';
aclr : in std_logic := '0';
clken : in std_logic := '1';
result : out std_logic_vector(widthr - 1 downto 0));
So, how should I write the port map if I want to add two input signals (eg dataa[15..0] and datab[15..0]) ?
Thank you !
Have a nice day !
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The altera_mf_logic_2D type is identical to the std_logic_2D type declared in the lpm-library. Unfortunately Altera hasn't declared any user functions/procedures to work with these types.
I started using the std_logic_2D type several years back to instantiate AHDL modules where you could use arrays like A[1..0][15..0] (which were represented by std_logic_2D by the generated VHDL components). As such I wrote quite some functions / procedures to work with std_logic_2D. Now a std_logic_2D is a true 2D type where you have a n by m array of (single) bits. This is different to 1Dx1D arrays where you have a vector of vectors. (see e.g. Volnei A. Pedroni: Circuit Design with VHDL page 30 and following).
In your case what you need (so far as I can see) is a simple procedure to map the two source std_logic_vectors to a std_logic_2D array:
procedure insert_std_logic_2D( signal destination : inout std_logic_2D ;
idx : in integer ;
source : in std_logic_vector )
is
begin
-- select maximum to provoke an error when not equal
for i in 0 to maximum(source'high , destination'high(2)) loop
destination(idx , i) <= source(i) ;
end loop ;
end procedure ;
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