Instantiating LPM Functions in VHDL: parallel adder

This is going to be complicated by the fact Altera uses the altera_mf_logic_2D type in this design (instead of just making an array of std_logic_vectors like any normal person would).

For a start, if you're just using two inputs, use the lpm_add_sub block instead, or just do an add in your code:

a <= b + c;

for parellel add, you have to map each bit individually to the bits on the bus, because of VHDL's strong typing. so:

data(0,0) => dataa(0);

data(0,1) => dataa(1);

--etc

data(1,0) => datab(0);

data(2,0) => datab(1);

For this stupid reason, I would be inclinded to write you own type conversion function:

function slv_to_alteras_stupid_2d_type( a : std_logic_vector; b : std_logic_vector) return altera_mf_logic_2D is
    variable ret : altera_mf_logic_2D(
begin
    for i in a'range loop
        ret(0,i) := a(i);
        ret(1,i) := b(i);
    end loop;
    
    return ret;
    
end function;

It could easily be modified to convert an array of std_logic_vectors into a 2d array type.