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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Instantiate VHDL Generics with Verilog code (for testbench)

Hello everybody.

When I instanciate inputs and outpus of a verilog code with verilog testbench I use following structure:

name_module MUT( .input_1(input_1),

.input_2(input_2),

.output_1(output_1),

.output_2(output_2)

);

And I instanciate params with this strucure:

defparam MUT.name_param = value.

But I have a problem when module under test is vhdl code and testbench is verilog code. ModelSim fail when I use defparam for instanciate generics vhdl.

in conclusion:

somebody can say me the instruction for instanciate generics vhdl with verligo testbench?

Thanks

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    Hi,

    Just use the normal verilog method 

    
 <module_name> 
#  ( <verilog parameters/vhdl generics> ) 
<instance_name> (
);

    You don't need to use defparam.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    Defparam is explicitly forbidden in the Modelsim User Manual for instantiating VHDL inside a Verilog testbench:

    --- Quote Start ---

    Generic Associations

    Generic associations are provided via the module instance parameter value list. List the values

    in the same order that the generics appear in the entity. Parameter assignment to generics is not

    case sensitive.

    The defparam statement is not allowed for setting generic values.

    --- Quote End ---