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Honored Contributor

8 years ago

Instantiate VHDL Generics with Verilog code (for testbench)

Hello everybody. When I instanciate inputs and outpus of a verilog code with verilog testbench I use following structure: name_modu...

Honored Contributor

8 years ago

Hi,

Just use the normal verilog method


 <module_name> 
#  ( <verilog parameters/vhdl generics> ) 
<instance_name> (
);

You don't need to use defparam.