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Altera_Forum
Honored Contributor
Honored ContributorInstantiate VHDL Generics with Verilog code (for testbench)
Hello everybody. When I instanciate inputs and outpus of a verilog code with verilog testbench I use following structure: name_modu...
Altera_ForumHonored Contributor
Honored ContributorHi,
Just use the normal verilog method
<module_name>
# ( <verilog parameters/vhdl generics> )
<instance_name> (
);
