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better use an HDL testbench to drive your inputs. That force statements, deposits is not that helpful and better be thrown in to the river.
e.g.
clk initialised to zero...
clk <= not clk after 5 ns;
rst <= '0', '1' after 1000 ns;
and so on...
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Thank you for the hint!! Probably my next obvious question now is, if you could recommend me one? I'm so happy to have found at least some possibility with ModelSim. Though it seems, if not re-opening it after an entire compilation, it shows some issues (line numbering might get messed up), but such things seem to be part of it, when working with FPGA / quartus ;)
Which HDL test bench would you recommend me?
Honored Contributor
