Input pin, without a driver.

Question

Hi all

I have a problem related to a thread (http://www.alteraforum.com/forum/showthread.php?t=26988)I once opened.

lets say I want an optional input pin, that is not always in use.

I used a generic that defines if the pin is used, and a generate statement that uses the pin (or not)

please see attached code

ENTITY my_dffe IS

GENERIC

(

RSTn_ON: BOOLEAN:= False;

BUS_WIDTH: INTEGER:= 1

);

PORT

.

END my_dffe;

ARCHITECTURE bdf_type OF my_dffe IS

SIGNAL RSTn_INT: STD_LOGIC;

BEGIN

RESET_ON: IF (RSTn_ON) GENERATE

RSTn_INT <= RSTn;

END GENERATE;

RESET_OFF:IF (NOT(RSTn_ON)) GENERATE

RSTn_INT <= '1';

END GENERATE;

.

END bdf_type;

this seemed to work fine when I used the schematic entry for the top level entity, so when I didn't want I the reset signal I simply didn't connect the pin and defined the generic as False.

when I tried to convert the top level entity to VHDL and compile I got error messages.

"formal port or parameter "RSTn" must have actual or default value"

"see decleration for object "RSTn""

anyone have any ideas?

thanks in advance

altera_forum · Answer

I assume RSTn is an input to this entity? basically, you havent connected it at the higher level.

altera_forum · Answer

Hi Tricky

I know I didn't connect it at the higher level, and I don't want to!

basically you can see that the pin drives no logic when the RSTn_ON generic is false.

when I compile the top entity as schematic entry, there is no problem.

then, I used the "create HDL design file from current file" command and tried to compile again, the I got these messages.

basically, what I want to achieve is something like the "PRN" and "CLRN" pins in the Quartus primitives such as DFF.

I hope I get myself clear...

altera_forum · Answer

Check the my_dffe component declaration in your top vhdl file. The default value for RSTn_ON may bemissing, I don't know how good Quartus' VHDL generation is.

altera_forum · Answer

The schematic entry tool will automatically connect unconnected inputs to GND I think. That does not happen in VHDL, and all inputs have to be specified - whether connected to a pin or '1' or '0'. I suggest you may need to put this generate at the top level.

altera_forum · Answer

Sorry I misread, I thought the warning was on the generic, not the pin. Just give a default value of '0' to RSTn and you'll have the same behaviour between the VHDL code and the schematic entry.

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Input pin, without a driver.

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