Forum Discussion
Altera_Forum
Honored Contributor
14 years agoHi Tricky
I know I didn't connect it at the higher level, and I don't want to! basically you can see that the pin drives no logic when the RSTn_ON generic is false. when I compile the top entity as schematic entry, there is no problem. then, I used the "create HDL design file from current file" command and tried to compile again, the I got these messages. basically, what I want to achieve is something like the "PRN" and "CLRN" pins in the Quartus primitives such as DFF. I hope I get myself clear...