input clock pin to 4 PLLs in a way Quartus is happy with

The reduced jitter performance of internally routed clocks is well described in the device manual. In so far the warnings are correct. The more interesting question is, if it's still sufficient for your application. In my opinion, a 400 MHz DDR3 interface is challenging as such, you should avoid additional risks and connect the dedicated clock input. For standard applications, you can more easily ignore the warning.