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Altera_Forum's avatar
Altera_Forum
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14 years ago

inout Std_logic_vector Signal Test

Hi, I am getting the following error by writting a testbench for Asynchrone SRAM and I have tried to solve this unsucessfully.Please any advice error output:# ** Error: Z:/Prototyp/Develo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

the SRAM controller could be part of their IP catalogue,, and the TCl connects it to the SRAM. TCL cannot be used directly to create an SRAM controller. It could generate the VHDL/verilog though.

Are you sure its not a verilog file?