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Altera_Forum
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14 years ago

inout Std_logic_vector Signal Test

Hi, I am getting the following error by writting a testbench for Asynchrone SRAM and I have tried to solve this unsucessfully.Please any advice error output:# ** Error: Z:/Prototyp/Develo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

be aware that "after" keywords only work in simulation. They will be ignored for synthesis.

The code you currently had will create millions of latches (more than is avaiulable in any device) because of the way you are connecting to the memory. Memory in FPGAs has to be synchronous, so you will have to have a clock input and follow the templates for infering a RAM.

This new code is not a controller, it is a RAM.