inout Std_logic_vector Signal Test

Please sorry I send the false one here is the rigth controller:

entity sram1024kx8 is
  port (A    : in Std_logic_vector(19 downto 0);
        D    : inout Std_logic_vector(7 downto 0);
        nCE : in std_logic;
        nCE2 : in std_logic;
        nWE : in std_logic;
        nOE : in Std_logic);
end;
architecture Behaviour of sram1024kx8 is
    subtype Byte is Std_logic_vector(7 downto 0);
    type Mem is array (0 to 1048576 ) of byte;
    signal Memory: Mem := (others => Byte'(others=>'U'));
    
begin
  process(A, D, nCE, nCE2, nWE, nOE)
  begin
    D <= (others => 'Z');
    if nCE='0' and nCE2='0' then
      if nOE = '0' then                  -- Read operation
        D <= Memory(To_Integer(unsigned(A))) after 10 ns;
      elsif nWE = '0' then               -- Write operation
        Memory(To_Integer(unsigned(A))) <= D;
      end if;
    end if;
  end process;
end;