inout Std_logic_vector Signal Test

The external memory I intend to implement in my FPGA Project is from CYPRESS(8-Mbit (1024 K × 8) Static RAM)

Here is my controller :

--- Quote Start ---

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

entity test_sram1024x8 is

PORT ( D : inout Std_logic_vector(7 downto 0));

end;

architecture test of test_sram1024x8 is

COMPONENT sram1024kx8

port (A : in Std_logic_vector(19 downto 0);

D : inout Std_logic_vector(7 downto 0);

nCE : in std_logic;

nCE2 : in std_logic;

nWE : in std_logic;

nOE : in Std_logic);

END COMPONENT ;

SIGNAL A : std_logic_vector(19 downto 0) := (others => '0');

SIGNAL nCE : std_logic := '1';

SIGNAL nCE2 : std_logic := '1';

SIGNAL nWE : std_logic := '1';

SIGNAL nOE : std_logic := '1';

--SIGNAL D : std_logic_vector(7 downto 0):="00000000";

begin

dut : sram1024kx8 PORT MAP (

A => A(19 downto 0),

D => D(7 downto 0),

nCE => nCE,

nCE2 => nCE2,

nWE => nWE,

nOE => nOE );

stimulus : PROCESS

begin

--A <= '0000';

wait for 5 ns;

--A <= (others => '0');

--wait for 25 ns; -- Read Task

nCE <= '0';

nCE2 <= '0';

nWE <= '0';

--Write the value "i" at the address "i" for 10 clock cycles.

for i in 0 to 10 loop

A <= conv_std_logic_vector(i,20);

D <= conv_std_logic_vector(i,8);

wait for 10 ns;

end loop;

nOE<= '0';

--Read the RAM for addresses from 0 to 20.

for i in 0 to 10 loop

A <= conv_std_logic_vector(i,20);

wait for 10 ns;

end loop;

end PROCESS stimulus;

end test;

--- Quote End ---

Is that enough to fully control my Cypress SRAM?

But there are also timing requirement on Cypress Datasheet?