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Altera_Forum
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14 years ago

inout Std_logic_vector Signal Test

Hi, I am getting the following error by writting a testbench for Asynchrone SRAM and I have tried to solve this unsucessfully.Please any advice error output:# ** Error: Z:/Prototyp/Develo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Well the problem is you have not constrained the signal A (please read your errors)

you need to give it a size. You can only constrain constants with an initialisation value.

signal a : std_logic_vector(19 downto 0) := (others => '0');