Forum Discussion
Altera_Forum
Honored Contributor
18 years agoWhere the web page you listed says "functional simulation", that means simulating with your RTL files. Your post said "simulate the post synt[h]esis netlist." If you are simulating with a .vo generated by Quartus, see the timing simulation link on the web page you listed.
With a .vo, the memory initialization data will be inside that file. The simulator won't use .mif or .hex files. (See http://www.alteraforum.com/forum/showthread.php?p=2154#post2154.)