Initial value priority

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I often use initial values on my vhdl signals (instead or in addition to reset) to ease simulation or to just initially specify signals or inferred memory content at power up. Now, if these signals are inputs optionally sourced by some other vhdl code, or even assigned to another signal with a different initial value, things still synth on quartus (no warnings?) and Im left being insecure of what initial value really got used..

Is there any guides on how this works/should work? Plain logic tells me the top level initialization should override any local, but Id like to see that documented.

The reason I ask is first because this always made me wonder, and second that I just cooked some code with dual port mem, where the access ports are in different vhdl code blocks, and the full array is passed between them, and even if I initialize on both sides, it seems to end up with all 0's at power up. It does infer as dual port mem as expected, but Im not sure what I need to do to initialize this. (I havent tried the .mif way, but I'd like to avoid it if I can).

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When it comes to synthesis, initial values only apply to registers at power up(& memory cells). Initial values on wires is useless though ModelSim respects them.

setting "powerup don't care' to off can be used to apply default zero powerup for all registers except those with preset values.

using code assignment := at signal declaration is nowadays supported for initial values on registers.

If the signal is not a register then it is ignored.

If you initialise a module input (din) with say zeros then wire it up to another module's output (dout) that is initialised to ones then you need to work out what registers you are going to get. Are you going to get two pairs one labelled din and the other dout? No

dout may be register but din does not refer to a different register. Even if you register din directly to din_r what you get is:

dout_reg => din => din_r_reg

As you can see the register is named by its output, not its input. So in above example I will assume the output initial value of ones will take over and din will acquire it as it wired to it. You can try it yourself in quartus and tell us.

Thanks kaz. I agree on your approach on the register level. Not sure how this will work on dual port inferred memory tho. I have seen it work as long as the memory array has both its ports accessed within the same entity, but it seems to fail if I wire the array outside and access 2nd port from somewhere else. Maybe its just a minor bug that never got caught.

btw, off topic, it was interesting to see your profile pic. I was visiting your land and some oil fields late last year. It was an interesting and peaceful visit and I know there are lots of interesting politics going on there right now. The Kurds seems to do very well in contrast to surrounding areas. I wish you and your people good luck! :) (PS:I do have economical interest in the oil business there)

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Thanks kaz. I agree on your approach on the register level. Not sure how this will work on dual port inferred memory tho. I have seen it work as long as the memory array has both its ports accessed within the same entity, but it seems to fail if I wire the array outside and access 2nd port from somewhere else. Maybe its just a minor bug that never got caught.

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You still have to declare and initialise the memory array in only one area even though you may access one port from one module, the second port from another module. It could be you are not following the inference methodology given by Altera.

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btw, off topic, it was interesting to see your profile pic. I was visiting your land and some oil fields late last year. It was an interesting and peaceful visit and I know there are lots of interesting politics going on there right now. The Kurds seems to do very well in contrast to surrounding areas. I wish you and your people good luck! :) (PS:I do have economical interest in the oil business there)

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Interesting small global village. I grow up there in the heights of oppression of the defenseless people in their sliced nation. Ironically that oil was used to buy tools of our destruction. Hopefully those days gone for ever. Thanks for your remarks and wish you and your business success.

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You still have to declare and initialise the memory array in only one area even though you may access one port from one module, the second port from another module. It could be you are not following the inference methodology given by Altera.

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On this matter, I tried to initialize at both ends one at a time, and even same initialization at both ends, but it all seems to initialize to 0, no matter what I do.

But going back to signals and wires.. If you initialize a wire and hook it up to a non initialized register, are you sure the init value doesnt traverse back to the register? I think I have to do my own testing on this area since its hard to find documentation.

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Interesting small global village. I grow up there in the heights of oppression of the defenseless people in their sliced nation. Ironically that oil was used to buy tools of our destruction. Hopefully those days gone for ever. Thanks for your remarks and wish you and your business success.

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The oil and gasfields I was visiting was the newer ones (in Dokuk and near Zakho, with the oil seeps), not the old ones that was used for your oppression. I'm almost daily keeping an eye on whats happening there :)

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On this matter, I tried to initialize at both ends one at a time, and even same initialization at both ends, but it all seems to initialize to 0, no matter what I do.

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I imagine I can only initialise memory array once and only when it is declared.

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But going back to signals and wires.. If you initialize a wire and hook it up to a non initialized register, are you sure the init value doesnt traverse back to the register? I think I have to do my own testing on this area since its hard to find documentation.

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I just did a quick test and noted (in ModelSim) that an initialised wire hooked back to a register does not propagate backwards and I was expecting that since any node is driven from its source only in one direction. I did fall into this sort of mistake before regarding the term "wiring". We normally think that wiring A to B in analogue sense implies A can drive B as well as B can drive A but this does not apply to digital logic and a statement of B <= A has one direction only unless you design it as bidirectional.

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The oil and gasfields I was visiting was the newer ones (in Dokuk and near Zakho, with the oil seeps), not the old ones that was used for your oppression. I'm almost daily keeping an eye on whats happening there :)

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Remarkable coincidence. Zakho is my birthplace and the oil village of Tawke is a place I frequently visited in childhood. It was then just tarred land and villagers used the tar for their night candles. It was not commercially exploited by the state then as it was too small and the state authority stopped at the edges of Zakho town, beyond which it was "liberated area" and launch base of old but accurate shells onto Zakho garrison of occupiers. However, I didn't know that later my fate would end up as state conscript in that very occupying garrison, totally confused.

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I imagine I can only initialise memory array once and only when it is declared.

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I must say Im confused, as in this case its hard to tell where it is declared, at port1 or port2.. Maybe synthesis is just as confused and dont care about init state :)

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I just did a quick test and noted (in ModelSim) that an initialised wire hooked back to a register does not propagate backwards and I was expecting that since any node is driven from its source only in one direction. I did fall into this sort of mistake before regarding the term "wiring". We normally think that wiring A to B in analogue sense implies A can drive B as well as B can drive A but this does not apply to digital logic and a statement of B <= A has one direction only unless you design it as bidirectional.

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I guess this way of thinking is only "graphically valid" if you draw a "wire" between the register output and the wire at next entity. My first thought was that a wire is just a wire, not a "semiconductor" and hence I thought it would be identical to register output, but Im probably wrong. Maybe synthesis should just refuse to set initial value to a wire.

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Remarkable coincidence. Zakho is my birthplace and the oil village of Tawke is a place I frequently visited in childhood. It was then just tarred land and villagers used the tar for their night candles. It was not commercially exploited by the state then as it was too small and the state authority stopped at the edges of Zakho town, beyond which it was "liberated area" and launch base of old but accurate shells onto Zakho garrison of occupiers. However, I didn't know that later my fate would end up as state conscript in that very occupying garrison, totally confused.

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Nice to hear history from the locals mouth! :) I missed that local history part on my visit. On my trip, the guides were mainly American and Norwegian oilbusiness men. We had a Kurd from Erbil with us but he told us more abour Kurdistan in general. I hope I can visit the area again one day with a different focus and more time on the hand :)

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I must say Im confused, as in this case its hard to tell where it is declared, at port1 or port2.. Maybe synthesis is just as confused and dont care about init state :)

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Here is a piece of Altera code for rom inference:

-- Declare the ROM signal and specify a default value. Quartus II
    -- will create a memory initialization file (.mif) based on the 
    -- default value.
    signal rom : memory_t := init_rom;
    
    begin
    
    process(clk)
    begin
        if(rising_edge(clk)) then
            q_a <= rom(addr_a);
            q_b <= rom(addr_b);
        end if;
    end process;
end rtl;

The reading of ports q_a or q_b can be across two modules but the rom array (called rom) occurs only once.

But I must be cautious here as templates for inference need to be adhered to well.

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I guess this way of thinking is only "graphically valid" if you draw a "wire" between the register output and the wire at next entity. My first thought was that a wire is just a wire, not a "semiconductor" and hence I thought it would be identical to register output, but Im probably wrong. Maybe synthesis should just refuse to set initial value to a wire.

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If I assign B <= A then in the final synthesis I expect both nodes will optimise to one and the notion of wire will vanish but at code level the compiler will need to look at how the user describes their drive. In this case no gating is involved and it seems it ignores initial value on B.

If additionally I assign A <= B then obviously I need first to resolve the double drive on A and the compiler I assume will propagate initial value of B to A according to my logic if it applies as initial state.

So my view is that A and B nodes exist as separate nodes first until the compiler realises that both are just identical at the end and require no gating but refuses to respect initial value on B.

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Nice to hear history from the locals mouth! :) I missed that local history part on my visit. On my trip, the guides were mainly American and Norwegian oilbusiness men. We had a Kurd from Erbil with us but he told us more abour Kurdistan in general. I hope I can visit the area again one day with a different focus and more time on the hand :)

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Thanks for your interest. Best time of visits would be spring March ~ June. Not summer as you will be attacked by armies of mosquitoes.

Please note my last edit :

But I must be cautious here as templates for inference need to be adhered to well.

This may explain why your initialisation fails