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I imagine I can only initialise memory array once and only when it is declared.
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I must say Im confused, as in this case its hard to tell where it is declared, at port1 or port2.. Maybe synthesis is just as confused and dont care about init state :)
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I just did a quick test and noted (in ModelSim) that an initialised wire hooked back to a register does not propagate backwards and I was expecting that since any node is driven from its source only in one direction. I did fall into this sort of mistake before regarding the term "wiring". We normally think that wiring A to B in analogue sense implies A can drive B as well as B can drive A but this does not apply to digital logic and a statement of B <= A has one direction only unless you design it as bidirectional.
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I guess this way of thinking is only "graphically valid" if you draw a "wire" between the register output and the wire at next entity. My first thought was that a wire is just a wire, not a "semiconductor" and hence I thought it would be identical to register output, but Im probably wrong. Maybe synthesis should just refuse to set initial value to a wire.
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Remarkable coincidence. Zakho is my birthplace and the oil village of Tawke is a place I frequently visited in childhood. It was then just tarred land and villagers used the tar for their night candles. It was not commercially exploited by the state then as it was too small and the state authority stopped at the edges of Zakho town, beyond which it was "liberated area" and launch base of old but accurate shells onto Zakho garrison of occupiers. However, I didn't know that later my fate would end up as state conscript in that very occupying garrison, totally confused.
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Nice to hear history from the locals mouth! :) I missed that local history part on my visit. On my trip, the guides were mainly American and Norwegian oilbusiness men. We had a Kurd from Erbil with us but he told us more abour Kurdistan in general. I hope I can visit the area again one day with a different focus and more time on the hand :)
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