Info Test bench Settings

In

Settings -> Simulation -> Test benches... -> New

windows, you can see a checkbox saying "use test bench to perform VHDL timing simulation".

What is this for?

I use QuartusII 10.0 web edition and both design and test bench are in Verilog.

If unchecked everything works. Also the gate level simulation (is this the same as a timing simulation?)

If, however, you want to generate the .VCD file you need to check it and specify your instance name in the test bench.

Why?

Is this something specific to VHDL?

thx.