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Altera_Forum's avatar
Altera_Forum
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14 years ago

inferring rams with read enable port ?

Hi to everyone, I'm trying to infer a tdpram with rden port , because I need the rden port I insert it in the entity and I tried to use the rden signal . I used the VHDL template for tdpram with mixe...
Altera_Forum's avatar
Altera_Forum
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14 years ago

You didn't yet answer about the intended function of the rd_en. Do you have a register holding previous values in your compatible projects?

As I already mentioned, it's impossible to have an synchronous output register and no additional delay of one clock cycle with Altera RAM blocks. You can either implement a transparent latch or a register with delay.