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Altera_Forum
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14 years ago

inferring rams with read enable port ?

Hi to everyone, I'm trying to infer a tdpram with rden port , because I need the rden port I insert it in the entity and I tried to use the rden signal . I used the VHDL template for tdpram with mixe...
Altera_Forum's avatar
Altera_Forum
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14 years ago

My question is possible to infer the read enable port in a Vhdl model for Altsyncram without using Altera Megawizard? In some our projects we had some rams generated with megawizard with an effective rden signal (not cabled to '1' value), for portability coding we want to infer Rams directly in VHDL code . Could give us an example of infering a ram with rden enable synthetizable by Quartus II?