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roberto_udc's avatar
roberto_udc
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4 years ago

Inferring DSP pre-adders and post-adders in VHDL

Hello, I have isolated my problem in a very simple piece of code:

entity pruebas is

port( a, b : in unsigned(26 downto 0);

b : in unsigned(7 downto 0);

res : out unsigned(53 downto 0));

end pruebas;

architecture RTL of pruebas is

begin

res <= a * (b + c);

end RTL;

I expected that Quartus Prime 16.1 would add “c” using the pre-adder before the multiplier in the DSP, but it’s using LUTs instead.

A very similar example (res <= (a*b) + c) also uses LUTs instead of a accumulator/adder at the end of the DPS. In this case, I made c larger, in the range of 30 bits.

Is there any trick or condition to fulfill in order that Quartus implements those sums using the available resources inside the DSP block? All user guides I've checked so far explain the capabilities of the devices, but I cannot find any actual implementation example.

I'm targeting an Arria 10 device, btw.

Thanks in advance,

Roberto

3 Replies

    • roberto_udc's avatar
      roberto_udc
      Icon for New Contributor rankNew Contributor
      4 years ago

      Unfortunately, my problem is slightly more complex and, somehow, the opposite one. Quartus uses one DSP to implement the product, but it wastes the possibility of implementing the addition inside the DSP.

      I’ve tried this:

      attribute multstyle of res : signal is "dsp";

      But Quartus uses 1 DSP plus 17 ALM. The latter could be saved, in my opinion.

      I think there must be a way to do it. I’ve tried with Vivado and the addition is performed inside the DSP, that is, one DSP and no LUTs. There should be a way to suggest Quartus to do the same.

      Best