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New Contributor

4 years ago

Inferring DSP pre-adders and post-adders in VHDL

Hello, I have isolated my problem in a very simple piece of code: entity pruebas is port( a, b : in unsigned(26 downto 0); b : in unsigned(7 downto 0); res : out unsigned(53 dow...

RichardT_altera

Super Contributor

4 years ago

Hi @roberto_udc

You may checkout this similar post with a detailed answer. Let me know if it helps.

https://electronics.stackexchange.com/questions/363915/avoid-using-dsps-in-quartus-prime

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.

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Inferring DSP pre-adders and post-adders in VHDL

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