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roberto_udc
New Contributor
New ContributorInferring DSP pre-adders and post-adders in VHDL
Hello, I have isolated my problem in a very simple piece of code:
entity pruebas is
port( a, b : in unsigned(26 downto 0);
b : in unsigned(7 downto 0);
res : out unsigned(53 dow...
RichardT_altera
Super Contributor
Super ContributorHave you checkout the KDB below and see if the VHDL template works for you.
https://www.intel.com/content/www/us/en/support/programmable/articles/000079100.html
Best Regards,
Richard Tan
p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.
