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If the RAM is inferred with unregistered addresses, as in the example (I guess so, the origin of address signal is hidden), Quartus has to turn registered output into registered addresses with unregistered output. This necessary conversion may hinder Quartus to realize the DP option.
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From the Quartus handbook, Volume 1, Section II, Chapter 6, under "ROM Functions—Inferring altsyncram and lpm_rom Megafunctions from HDL Code":
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For device architectures with synchronous RAM blocks, such as the Stratix series devices and newer device families, either the address or the output has to be registered for ROM code to be inferred. When output registers are used, the registers are implemented using the input registers of the RAM block, but the functionality of the ROM is not changed.
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I still suspect that the limitation the original poster ran into is just what I said earlier about QIS not supporting all possible control signals for inferred memories.
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I would try to define the logic with synchronous addresses and asynchronous output as in the Quartus manual inference example.
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My test used Quartus handbook, Volume 1, Section II, Chapter 6, Example 6-25. (I filed a service request for this example missing the needed "end rtl;" at the end and otherwise having everything shown twice.) This handbook example is very similar to the one in this thread with the RTL implying that the only registers are on the output, so Quartus moved those registers to the address inputs for my test.
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