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Altera_Forum
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17 years ago

Inferring DP-ROM

I’d like to infer a 2-port ROM with a read-enable signal using VHDL. Without the read-enable everything is o.k.. Using the read-enable, Quartus use a single ported ROM with the double size instead of...
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Altera_Forum
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17 years ago

Brad is right, Cyclone III has a read enable.The problem is probably a different one. Synchronous RAM/ROM has always registered addresses and optionally registered output.

If the RAM is inferred with unregistered addresses, as in the example (I guess so, the origin of address signal is hidden), Quartus has to turn registered output into registered addresses with unregistered output. This necessary conversion may hinder Quartus to realize the DP option.

I would try to define the logic with synchronous addresses and asynchronous output as in the Quartus manual inference example.