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jal_joshi's avatar
jal_joshi
Icon for New Contributor rankNew Contributor
4 years ago
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Inferring a True Dual Port RAM with Byte enable for MAX10 FPGA

I'm trying to implement a True Dual Port RAM with byteenable for MAX10 FPGA. When I try synthesizing the code it gets inferred as an SYNC_RAM (RTL Viewer) but without byte enable as one of its ports....
  • ShengN_altera's avatar
    ShengN_altera
    4 years ago

    Hi,


    The reason why there are 4 M9K blocks is because of mem_byte0, mem_byte1, mem_byte2 and mem_byte3 you declared.

    May go to Edit -> Insert Template -> Verilog HDL -> Full Designs ->RAMs and ROMs and refer to True Dual Port RAM (dual clocks).

    May also go to Edit -> Insert Template -> VHDL -> Full Designs ->RAMs and ROMs and refer to Byte-enabled True Dual Port RAM for byte enable. (VHDL)


    Thanks,

    Best regards,

    Sheng

    p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.


ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
4 years ago

Hi,


The reason why there are 4 M9K blocks is because of mem_byte0, mem_byte1, mem_byte2 and mem_byte3 you declared.

May go to Edit -> Insert Template -> Verilog HDL -> Full Designs ->RAMs and ROMs and refer to True Dual Port RAM (dual clocks).

May also go to Edit -> Insert Template -> VHDL -> Full Designs ->RAMs and ROMs and refer to Byte-enabled True Dual Port RAM for byte enable. (VHDL)


Thanks,

Best regards,

Sheng

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos.