Inferred latches for variables

Guys, my search for solution shows that 74*373 chip type is not possible to model in hardware. Please confirm, or provide the working example of the transparent latch, which works IN SILICON.

- There're lots of exapmles of the transparent latch on the web (including wikipedia, which, while is not accepted by academics as reliable source, is deemed as one of the publicly validated source);

- FvM says "you have a counter without a clock. It will never work in hardware Verilog, although it possibly gives meaningful results in a functional simulation."

- Some XILINX document also says "Most Xilinx FPGAs do not support latches very well. If your code includes latches either intentionally or

by accident, you will get a warning about “latch inferred in design” and should remove them."

I get this warning. I am not sure it works properly after FvM's comment. I need to be sure that it works as I expect.