Inferred latches for variables

Sorry, but I don't exactly understand what you try to achieve. In you're above code, there is no CLK input signal. For this reason, I suggested to use trigger as a clock with a posedge condition. What's wrong when you do this?

I forgot to mention, that the if (trigger == 1) condition must be removed with posedge trigger, otherwise it's still an asynchronous event.

always@(trigger)
begin
count = count + 1;
// ....
end

The event condition of an always block can be either asynchronous (creates combinational logic) or synchronous (creates flip-flops). But only one event condition can be in effect for a particular code block.

If you want to detect a rising edge of the trigger input but not use trigger as a clock, you can perform a synchronous edge detection in your main clock domain.

reg trigger_sync, trigger_s_prev;
always @(posedge CLK)
begin
  trigger_sync <= trigger;
  trigger_s_prev <= trigger_sync;
  if (trigger_sync && !trigger_s_prev)
    count <= count + 1;
  case (count)
  endcase
end