Inferred latches for variables

No that is not possible.

What is possible, and correct, is to write it like this:

always@(posedge CLK) begin : detect_trigger
   if (trigger) begin : trigger_active_at_clk_rising_edge
     count <= count + 1; // count up
   end
end

This produces FPGA friendly code. But it will only work if trigger is active longer than on clk cycle period and less than two clk cycle periods.

If you want it to also work when trigger is active for longer periods, than you need to store a auxiliary state variable trigger_d

always@(posedge CLK) begin : detect_trigger
   logic trigger_d;
   if (trigger & ~trigger_d) begin : trigger_active_at_clk_rising_edge
     count <= count + 1; // count up only at the rising edge of trigger
   end
   trigger_d <= trigger; // delay it one clk cycle in order to look into the past
end