Since I'm not exactly sure what you are trying to do I'll give this advice:
- Don't assign anything to an integer type (I'm not sure if all synthesis tools will behave the same .... considering I've never seen someone attempt this before)
- Don't mix case and if statements in a single always block
- Control a-j independently (separate always blocks)
- If you intended to use registers use a clock edge for the always block and use enables to control when values get registered by the flip flop
I could keep making suggestions but I think it would be quicker if you just describe what you are attempting to synthesize. If you go into Quartus II with your verilog file open and select from the edit menu "Insert Template" you'll see all kinds of pre-cooked templates for writing various logic blocks. I also recommend taking a look at this document, it'll explain the various cases when you get a latch out of synthesis and how to avoid it.
http://www.altera.com/literature/hb/qts/qts_qii51007.pdf
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