Inferred latches for variables

Did you possibly mean to write an edge sensitive always block? An always block without a posedge or negedge event expression generates only combinational logic. Most likely it doesn't work as you intended.

At begin of the block, you have a counter without a clock. It will never work in hardware Verilog, although it possibly gives meaningful results in a functional simulation.

always@(trigger)
begin
if(trigger == 1)
count = count + 1;

Consider, what you want to achieve and consult a Verilog textbook or Quartus Verilog templates about how it can be coded.

As a first attempt, you can just try

always @(posedge trigger)