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Altera_Forum's avatar
Altera_Forum
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18 years ago

Incrementing a vector

I'm using behavioral vhdl to make a finite state machine and I'm running into a simple problem I think.

This is what my code looks like: 

PC: OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
<some more code>
BEGIN
    PROCESS(clock)
    BEGIN
        IF Reset = '1' THEN
            state<=A;
	    PC<="0";
<some more code>
			
         WHEN B=>
	    PC <= PC + 1;
<some more code>

It says that interface object "PC" of mode out cannot be read. Change object mode to buffer. What does that mean?

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    Hello,

    to read back the port signal in the entity, you must redefine the output port 

    PC: BUFFER STD_LOGIC_VECTOR(15 DOWNTO 0);

    When instantiating the entity as component, you can still use OUTPUT definition.

    "Incrementing" a vector, which seems mathematical unreasonable, is only possible when importing STD_LOGIC_UNSIGNED or STD_LOGIC_SIGNED library.

    Regards,

    Frank
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Some companies shy away from the type BUFFER, and just create an intermedieate SIGNAL called PC_sig or something, and do all the calculations with that, and end the code with:

    PC <= PC_sig;

    That way PC never ends up on the right side of a "gets" statement. Personally, I haven't had any qualms about using the BUFFER type.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    Hello,

    with Quartus synthesis, I wouldn't expect different netlist results with BUFFER mode of interface versus OUTPUT mode with an extra "wire" signal. However, if you want to hide BUFFER mode in component declaration and to reuse the entity port declaration for the component, e. g. cause it is generated automaticly by a script, than you have to use wire signals.

    Regards,

    Frank
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    Buffer or

    Use an intermediate signal in architecture.

    Ex. :

    signal PC_i : STD_LOGIC_VECTOR(15 DOWNTO 0);

    begin

    ...your state machine with PC_i ...

    PC <= PC_i;

    ...

    end architecture;