Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Incrementing a vector

I'm using behavioral vhdl to make a finite state machine and I'm running into a simple problem I think. This is what my code looks like: PC: OUT STD_LOGIC_VECTOR(15 DOWNTO 0); <some more co...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Some companies shy away from the type BUFFER, and just create an intermedieate SIGNAL called PC_sig or something, and do all the calculations with that, and end the code with:

PC <= PC_sig;

That way PC never ends up on the right side of a "gets" statement. Personally, I haven't had any qualms about using the BUFFER type.