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Altera_Forum
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17 years ago

Incorrect Latch Edge in Timequest

I have a design which uses a PLL that introduces a phase shift of 625ps between the incoming clock and the PLL output clock. Timequest determines that the Launch edge is the incoming clock and...
Altera_Forum's avatar
Altera_Forum
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17 years ago

set_multicycle_path -setup -from [get_clocks clk_a] -to [get_clocks phase_shifted_clk] 2

That will shift the setup latch edge out one cycle, and the hold edge will move too. (In other words, you now have a positive 625ps hold requirement).

Just as importantly, are you transferring data from the non-PLL clock coming in on the FPGA port to the PLL phase-shifted domain? If so, you're going to have all sorts of timing issues. What I would recommend is making the PLL have two outputs, one phase-shifted and one not, and they will have similar clock delays that cancel out, i.e. the two clocks will really be about 625ps off from each other.