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Altera_Forum's avatar
Altera_Forum
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12 years ago

include file in a vhdl file ...

Hi, I need to include a computer generated vhdl file (including constants) in another vhdl file. I could generate the full file (so the header etc etc ) with my C code, but would be more clean...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

you define a package called constants and use it like you did the other libraries

Use work.constants.all;

There is no pre-processor in VHDL like there is in C or Verilog, so you cannot just include another load of text. It has to be a compiled package.

PS, Why are you using the non-standard std_logic_unsigned library?