In verilog when the default case in a case statement is ignored by synthesis

Thanks for the reply, here is the problem. If timing is always met, the state variable will never have any unused states. The problem is timing is not always met in the communications world. You have external and internal plls acquiring lock and during that process, they may output a frequency that violates timing. I have a rule when coding logic. And that is you should be able to jam any set of values into any set of registers (other than micro processor controlled), let the system run and it will eventually return to normal. Logic that can get into a stuck state and stay there is very bad especially when it happens at a customer sight. Altera is touting an experiment where a car is being driven by a cyclone device. I would not want to be on the road with that car if the cyclone logic could get into a bad state and not recover. Altera calls it optimization, I call it re writing my code. A couple of days ago I looked at the difference in one of our chips between safe FSMs and unsafe. The additional logic usage was negligible and the design had over 100 state machines. On the other hand, this (unsafe) issue has caused a near stop shipment on one of our products.