In-system memory content editor cannot read/write to RAM

The In-system memory content editor cannot read or write a RAM that was instantiate for the IP core library.

The RAM (altsyncram) concerns a single port configuration. Read and write commands from other (own) blocks is going well, but the content editor gives a depth of 0 addresses of the RAM.

I have already added the default parameter: CYCLONEIV_SAFE_WRITE RESTRUCTURE, but it didn't work out anything.

In the RTL and technology viewer, the RAM block is connected to the JTAG logic.

Used soft- and hardware:

Quartus II Version 14.1.0 Build 186 12/03/2014 SJ web edition

DE0-nano / FPGA: EP4CE22F17C6

VHDL code:

altsyncram_component : altsyncram
    GENERIC MAP (
        clock_enable_input_a => "BYPASS",
        clock_enable_output_a => "BYPASS",
        intended_device_family => "Cyclone IV E",
        lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=RAM",
        lpm_type => "altsyncram",
        numwords_a => 32,
        operation_mode => "SINGLE_PORT",
        outdata_aclr_a => "NONE",
        outdata_reg_a => "UNREGISTERED",
        power_up_uninitialized => "FALSE",
        read_during_write_mode_port_a => "DONT_CARE",
        widthad_a => 5,
        width_a => 8,
        width_byteena_a => 1
    )
    PORT MAP (
        address_a => address,
        clock0 => clock,
        data_a => data,
        wren_a => wren,
        q_a => sub_wire0
    );

Anyone an idea why I cannot read/write with the in-system memory content editor?

Thank you in advance,

Rutger