In A10/C10 hard ip for PCIe, size of address pages can't be 128KB to 2MB

Hi Nathan,

Thank you very much.

Now I still not clear how high PCIe address bits are determined, when Address width of accessible PCIe memory space is LESS than 64.

My solution is:

set AVMM address width = 64, and set Address width of accessible PCIe memory space = 64

writing a dedicated component to master txs point-to-point, it controls all 64 address bits of txs.

at the same time, the component is an MM slave too. the host will tell it where the dma buffer is thru a BAR.

the txs can NOT be connected to the main QSYS directly, because it will occupy ALL address space.

it does work, but it looks a little stupid.

Regards

Jiang Wanli