Improving compilation time

Hello everyone, I've been trying to improve the compilation time of the "Video Processing Reference Design" for a while. This design has a quite big system generated by SOPC Builder with a NiosII, DDR2 controller, and several IPs from the "Video and Image Processing Suite". The compiling process takes more than 1h20m in a PC with an i7Q820 processor and 4GB of RAM. I’m following the incremental compiling flow without any improvement.

I set a simple design hierarchy with a schematic top level and two sub entities, one containing the reference design and another for extra logic. Each was set as a partition with a specific LogicLock region.

The problem is that, even a minor change inside of the extra logic partition, all system is regenerate, taking another hour or more. I’ve already tried several partition configurations (post-synthesis, post-fit…) but the results are almost the same.

I don’t know if a SOPC Builder system is really compatible with the Incremental Compilation as the guides claim.

Any ideas on how to improve the compilation time of a SOPC Builder system would be greatly appreciated.

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i7Q820 (4 cores)/4GB RAM

Quartus II 64-Bit Version 9.1 Build 350 03/24/2010 SJ Full Version

Service Pack Installed: 2