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wayne's avatar
wayne
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6 years ago

Import tcl-script to Quartus

After creating the list of modifications in the ECO file using Change Manager in Chip Planner, I exported the modifications as a tcl file.

But I can’t import this file into the project. After starting it through the TCL sripts built-in utility, an error appears on the command line:

<Error: ERROR: Unable to find Chip Planner netlist. Read the netlist by using the "read_netlist" command.>

Inside the tcl file, the read_netlist command is executed. And of course I am doing a full compilation of the project before this

16 Replies

  • wayne's avatar
    wayne
    Icon for New Contributor rankNew Contributor

    Then you need to do a series of actions, which I described in my message with screenshot. When changing the structure of one of the area, you will get a fitter error

  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    Icon for Regular Contributor rankRegular Contributor

    Hi,

    I checked the cells in Region_0 and Region_1; all of them are in Arithmetic operation mode. May I know in which module you modify the cell?

    Thanks.

  • wayne's avatar
    wayne
    Icon for New Contributor rankNew Contributor

    Hi,

    For example, the problem occurs after deleting the last cell in region 0, and the first cell in region 1. I want to connect them directly through carry chain. I guess the problem is not with LogicLock itself, but with the principles of the LE structure.

  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    Icon for Regular Contributor rankRegular Contributor

    Hi,

    Can you share how do you perform the below changes steps by steps in details including the cell name, signal name and node name?

    I need each adder to be connected via Cin / Cout carry chains and not through Combout / DataABCD.

    As a result of the corrections in the Resource Property Editor, I delete the LEs that work in normal mode and connect each LAB through the carry chains.

    Thanks.

  • wayne's avatar
    wayne
    Icon for New Contributor rankNew Contributor

    Hi,

    1) I delete the last LE from Region0 "result_int[15]~30"

    2) I delete the first LE from Region1 "result_int[0]~1"

    3) I connect the COUT of the penultimate LE from Region0 "result_int[14]~29" to the CIN of the second LE from Region1 "result_int[1]~3"

    As a result, I want to get two adders connected only by a carry chain

    To do the above operations, you can run the updated script.

  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    Icon for Regular Contributor rankRegular Contributor

    Hi,

    Yes. You are correct. The logic lock region assignments are removed when the nodes in a carry chain assigned to a logic lock region is assigned to some of the nodes in a carry chain in another location. To place the carry chain correctly, the Fitter removed the Logic Lock region assignments on the nodes in the carry chain.

    Thanks.