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possibly - what does your testbench say?
as a small not, you shouldnt really AND anything with the clock - it might create you some async logic with the clock.
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I'll remember to remove the ANDing.
I haven't had a chance to do a testbench yet. I've recently discovered the Mega-Wizard plug-in feature and have replaced everything with things generated from that. The only part I've not converted structurally is the actual "bouncing" portion of the circuit.
My thought is to use a 4-to-2 MUX.... but I'm trying to think about how I can switch my overall output to come from the MUX or from a "bouncer" which takes input from the MUX when the MUX Sel is "01" (Bounce the input).
For bouning, I guess I'm needing to use an inverter and then a latch.... maybe something SR instead? Either way, there seems to be an abundance of debouncing stuff on VHDL but nothing out there to simulate relay bounces via VHDL.
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