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If its just a behavioural model, then waits and the like are fine and encouraged to improve sim speed. But in you code you have no wait in your while loop, so it will be an infinite loop in 0 time if interval is greater than 0 when it enters the loop. This is because of the mechanics of vhdl. Signals are only updated when a process suspends eg on a wait.
there are other unusual things in you code, like updating tempq and last interval value outside of the reset or clock branches, so the will be assigned on any change of clock or clear.
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Good points.
Perhaps I should have done it this way?:
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architecture behavioral of bounce_processor is
signal tempQ: std_logic;
signal lastIntervalValue: std_logic_vector(4 downto 0);
begin
tempq <= d;
lastintervalvalue <= interval; process(clock, clr)
begin
if(clr = '1') then
q <= '0';
elsif (rising_edge(clock) and start = '1') then
if opcode = "000" then
q <= '0';
elsif opcode = "001" then
--initial bounce pulse when kicked off
q <= not tempQ;
tempQ <= not tempQ;
if (interval > "00000") then
-- complement pulse only when interval value changes
if (interval /= lastIntervalValue) then
q <= not tempQ;
tempQ <= not tempQ;
lastIntervalValue <= interval;
end if;
-- ensure final output is a complent of d regardless of pulses
elsif (interval = "00000") then
q <= not d;
end if;
elsif opcode = "010" then
q <= '1';
elsif opcode = "011" then
q <= '0';
end if;
end if;
end process;
end behavioral;
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