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It is all verilog, but the theory is the same (and reading verilog would be more up your street if you're a programmer)
Also study the coding guidelines in the quartus manual. Lots of code examples and templates in there.
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For what it's worth, this is the behavioral model of what I'm trying to do (I've got a block diagram below if it's easier to follow):
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architecture behavioral of bounce_processor is
signal tempQ: std_logic;signal lastIntervalValue: std_logic_vector(4 downto 0);
begin
process(clock, clr)
begin
tempQ <= d;
lastIntervalValue <= interval;
if(clr = '1') then
q <= '0';
elsif (rising_edge(clock) and start = '1') then
if opcode = "000" then
q <= '0';
elsif opcode = "001" then
--initial bounce pulse when kicked off
q <= not tempq;
tempq <= not tempq;
while (interval > "00000") loop
-- complement pulse only when interval value changes
if (interval /= lastintervalvalue) then
q <= not tempq;
tempq <= not tempq;
lastintervalvalue <= interval;
end if;
end loop;
-- ensure final output is a complent of d regardless of pulses
q <= not d;
elsif opcode = "010" then
q <= '1';
elsif opcode = "011" then
q <= '0';
end if;
end if;
end process;
end behavioral;
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https://www.alteraforum.com/forum/attachment.php?attachmentid=7394
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