Illogical comparator output

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With this:

process(le)

begin

if( le = '1' ) then

q <= d;

end if;

end process;

inferred a flip-flop d without usign 'event clause.

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Hard to believe and against all known RTL synthesis rules, e.g. IEEE 1076.6.

Which Quartus version did you see to infer a DFF from the code?

Of course, in functional simulation q would be only changed on rising edge of le, due to the missing d in sensitivity list. But in synthesized hardware, it will be still acting as a latch.