Illogical comparator output

You're right Tricky. I confused inferred latch with another concept. When you ommitted a signal in sensitivy list, like:

process(a)

begin

c <= a or b;

end process;

It seems like we're trying to describe some kind of inferred memory because a change on b not change the output. This was I was thinking.

As you said, Quaryus implement latches. I saw a technoloy map viewer and there are a subtle difference in how Quartus understand the code:

process(le, d)

begin

if( le = '1' ) then

q <= d;

end if;

end process;

This version inferred a latch.

With this:

process(le)

begin

if( le = '1' ) then

q <= d;

end if;

end process;

inferred a flip-flop d without usign 'event clause.