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In practice, the synthetizer can't implement inferred latches, so your circuit keeps combinational, but simulation stills shows the inferred latch behavior. So, in this case, simultation behaves different from real fpga operation.
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Wrong. The synthesisor can generate you infered latches, as the origional code does. And it will warn you about it.
To avoid latches, you need to make sure all if statements have an else inside asynchronous processes. The sensitivity list is for simulation only, and in the OPs case this solved the code not working problem, but would have worked as expected on hardware as the synthesisor ignores senstivity lists.
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